Integrated circuits can typically include various layers of conductive, semiconductive, and/or insulating materials. For example, an integrated circuit may include a substrate in which a number of active devices (such as transistors) may be formed. Such active devices may then be connected to one another by one or more conductive or semiconductive layers. The interconnecting conducting layers may be separated from one another by insulating layers.
Insulating layers typically provide electrical isolation between conductive layers. While insulating layers can be formed from a variety of materials, one consideration in selecting an insulating material can be the dielectric constant of the material. If a high dielectric constant material isolates a conductive line from a substrate, "parasitic" capacitance and/or transistor effects can occur.
Conductive or semiconductive layers may be formed from a single layer of material, or alternatively, include one or more conductive (or semiconductive) materials. As just a few examples, such a layer can include a conventionally doped polycrystalline silicon (polysilicon) and "silicide" (silicon-metal alloy). Alternatively, a conducting layer can include a titanium(Ti)-tungsten(W) alloy layered onto bulk aluminum, with an underlying barrier layer comprising Ti, Ti-nitride (TIN), or a Ti alloy. Similarly, insulating layers can also be composites. As just one example, an insulating layer may include a "doped" silicon dioxide ("oxide") and an "undoped" silicon oxide (undoped silicate glass or "USG"). The doped silicon oxide can include dopant elements, such as boron and phosphorous, while the undoped silicon oxide will be essentially free of dopant elements. Phosphorous doped silicon dioxide (phosphosilicate glass or "PSG") can provide advantageous ion gettering and step coverage properties. Boron and phosphorous doped silicon dioxide (borophosphosilicate glass or "BPSG") can also provide such advantages, and can be formed at lower temperatures.
Different conductive or semiconductive layers can be connected to one another by contacts and/or vias. Contacts and/or vias can include contact holes that extend through one or more insulating layers. Conventionally, contacts can connect a substrate to a conductive or semiconductive layer, while a via can connect two different conductive or semiconductive layers to one another.
A conventional way of forming a contact hole in one or more insulating layers can include lithography and etch steps. Lithography can be used to form a pattern over an insulating layer (that includes the location of contact holes). An etch step can transfer the pattern onto the insulating layer.
One concern with certain contact structures can be the alignment of a contact with a lower conducting layer. Because a contact is usually formed by etching a hole through an insulating layer to an underlying conductive or semiconductive, it is desirable for the etched hole to be situated directly over the desired contact location in the lower conducting layer. Further, it may be desirable to ensure that a contact hole can be sufficiently insulated from other conductive lines. For example, in the case of semiconductor devices having insulated gate field effect transistors (IGFETs), such as metal-oxide-semiconductor FETs (MOSFETs), it is desirable to have a contact hole aligned with a source or drain, but at the same time, be sufficiently insulated from a gate conductor.
Another concern regarding contacts and/or vias can be the area of the contact. The area of a contact can be of concern as a substrate on which a contact is formed can also include other important features, such as transistor channels, transistor isolation structures, transistor diffusion regions, and/or device wells. Thus, reductions in contact size can provide more area for other features and/or reduce the overall size of an integrated circuit device. Further, in many processes contact area may have a minimum requirement in order to ensure a low enough contact resistance value. Thus, it is desirable that a contact forming process be capable of meeting a minimum contact resistance value.
Various factors may contribute to reducing contact area. One such factor is that of contact aspect ratio (AR). An aspect ratio can describe the ratio between a contact height and width, when viewed in cross section. The higher the aspect ratio, the more difficult it may be to form the contact.
To better understand the formation of certain integrated circuit structures, including contacts and contact holes, a conventional self-aligned contact (SAC) approach is set forth in FIGS. 5 and 6A-6G. FIG. 5 is a flowchart illustrating the general steps involved in forming a self-aligned contact for an integrated circuit that includes MOSFETs. FIGS. 6A-6G set forth a number of side cross-sectional views of a portion of an integrated circuit following the various steps described in FIG. 5.
The conventional process set forth in FIG. 5 is designated by the general reference character 500. The process 500 can begin by forming MOSFET gate stacks having sidewalls (step 502). A portion of an integrated circuit following step 502 is set forth in FIG. 6A. A MOSFET gate stack 600 can be formed on a substrate 602, and include a gate oxide 604, conductive portions 606, and an insulating portion 608. Sidewalls 610 are also set forth in FIG. 6A.
It is noted that a substrate 602 can include isolation structures formed therein by a previous substrate isolation structure forming step. As just two examples, a substrate 602 can include shallow trench isolation structures and/or local oxidation of silicon (LOCOS) structures. Further, a substrate 602 may also include doped portions formed with previous and/or subsequent doping steps, such as transistor sources, drains, channels, and device wells.
A conventional process 500 can continue with the deposition of an insulating layer of BPSG and USG (step 504). A portion of an integrated circuit following step 504 is set forth in FIG. 6B. Referring now to FIG. 6B, the integrated circuit portion includes a BPSG layer 612 and an USG layer 614 formed over the BPSG layer 612. The BPSG and USG layers (612 and 614) may be formed over MOSFET gate stacks 600 and may be deposited using chemical vapor deposition (CVD) methods.
The conventional process 500 can continue with lithography and etch steps. A photoresist layer can be deposited on a USG layer 614 (step 506). Referring to FIG. 6C, an example of a portion of semiconductor device following a step 506 is shown in a side cross sectional view. A photoresist layer ("resist") can include a photoresist material 616 and a bottom antireflective coating (BARC) 618.
The photoresist material 616 can be patterned (step 508). Typically, a photoresist material 616 can be patterned by selectively exposing portions of the photoresist material to a radiation source. Typically a photomask can be used to establish the pattern. Radiation sources can include various light sources, including coherent light, from various spectrums including the visible spectrum and ultraviolet spectrum. Other methods can utilize X-rays, electron beam (e-beam), or ion beams to form a pattern in a photoresist material 616, to name but a few examples. E-beam and ion beam systems may not require a photomask.
A BARC 618 can reduce deleterious "corner" effects and/or other undesirable developing artifacts that may occur with smaller geometry devices.
Portions of the photoresist material 616 can then be removed according the pattern developed by the exposure to radiation. A portion of a semiconductor device after removal of photoresist material is shown in FIG. 6D. Once selected portions of the photoresist material 616 are removed, the photoresist material 616 can be "baked" to form an etch mask. In this way, in a conventional process 500, photoresist material serves as an etch mask.
A photoresist material 616 can have a predetermined thickness when deposited. Consequently, a resulting etch mask can also have a predetermined thickness. In the example of FIG. 6D, the photoresist etch mask exposes portions of the BARC 618, below which a contact hole may be formed.
Once an etch mask of photoresist is formed, a conventional process can then remove those portions of the BARC 614 and USG 614 that are situated below openings in the photoresist etch mask (step 510). A portion of a semiconductor device following the removal of a BARC 618 and USG layer 614 is shown in FIG. 6E.
A conventional process 500 can proceed with a SAC etch (step 512). FIG. 6F shows a portion of semiconductor device following a SAC etch. A SAC etch can form etch holes 620 that extend through a BPSG layer 612 to a substrate 602. As shown in FIG. 6F, the resulting contact holes 620 may be "self-aligned" with the MOSFET gate stacks 600. The self-alignment occurs by the insulating portions 608 and sidewalls portions 610 insulating conductive portions 606 from contact holes 620. As a result, a minimum spacing requirement between the edges of a contact hole 620 and a MOSFET gate stack 600 may not be necessary.
A conventional SAC etch can have a high degree of selectivity between a photoresist etch mask and a BPSG layer 612. That is, the rate at which BPSG can be etched may be substantially faster than the rate at which the photoresist etch mask can be etched.
A conventional process 500 can continue by removing a photoresist etch mask (step 514). A photoresist etch mask can be removed with a plasma etch that etches photoresist at a substantially faster rate than other exposed semiconductor device materials. Such a removal of a photoresist etch mask with a plasma etch is often referred to as "ashing."
While the described conventional process may produce desired contact holes at certain geometries (i.e., certain contact widths), as semiconductor device manufacturing processes provide smaller and smaller features, such conventional contact approaches may be inadequate. Smaller contact feature sizes may result in larger aspect ratios.
As just one example, a semiconductor device fabricated according to a conventional approach may include contacts of about 0.30 .mu.m. Such a contact formed adjacent to some MOSFET gate stacks can have an aspect ratio of about 2.5:1. However, when a contact hole is considered with its corresponding photoresist etch mask, its aspect ratio can be larger. This can best understood with reference to FIGS. 6F and 6G. In FIG. 6G a contact hole 620 that does not include the photoresist mask can have an aspect ratio of about 2.5:1. If a photoresist etch mask is included as part of a contact hole, as shown in FIG. 6F, a contact hole 620 can have an aspect ration of about 5:1.
Accordingly, if contact size decreases while photoresist etch mask thickness remains the same (or does not decrease proportionally), contact hole aspect ratios may increase to the point where a contact hole cannot be formed. This is illustrated in FIG. 7 which shows a side cross sectional view of an attempted formation of contact holes 720. Contact holes 720 (when photoresist mask portions are included) have too high a desired aspect ratio. In the particular example of FIG. 7, contact holes 720 are formed partially through a BPSG layer 712 and fail, as they do not expose a portion of a substrate 700. A contact hole may also fail by not providing sufficient contact area (i.e., exposing a sufficient amount of substrate area).
Alternate conventional etch processes can form contact holes without etch masks formed from photoresist. Such approaches include "hard" etch masks. Conventional hard etch masks may be etch masks formed from a deposited material that itself can be etched into a desired pattern. Nitride and polysilicon are two conventional hard mask materials. Polysilicon can be undesirable as a hard mask because it can be difficult to remove after it is used. Nitride can be undesirable as a hard mask because it can introduce a relatively high dielectric constant material between conductive layers.
In light of the conventional approach set forth above, it would be desirable to provide a way of forming contacts that can overcome the drawbacks described above.
It would also be desirable to form such contacts through an insulating material that includes PSG and/or BPSG, and therefore include the advantages of such materials.
It would further be desirable that such contacts be self-aligned contacts for an IGFET, as IGFET contact size can play an important role in reducing the overall size of an integrated circuit.
It would further be desirable that such contacts have relatively small geometries, for example 0.25 .mu.m or less, or more desirably, 0.18 .mu.m or less.